Thread Level Parallelism – SMT and CMP – Computer Architecture
Instruction-Level Parallelism - an overview | ScienceDirect Topics
Instruction Level Parallelism
Limits to ILP How much ILP is available using existing mechanisms with increasing HW budgets? Do we need to invent new HW/SW mechanisms to keep on processor. - ppt video online download
Instruction-Level Parallel Processors {Objective: executing two or more instructions in parallel} 4.1 Evolution and overview of ILP-processors 4.2 Dependencies. - ppt download